1. Field of the Invention
The present invention relates generally to semiconductor package technology and, more particularly, to a package stack structure and a manufacturing method thereof.
2. Description of the Prior Art
Stacking technology may generally be classified into a chip stacking method or a package stacking method. On the one hand, the chip stacking method may have an advantage in terms of overall size (e.g., the thickness of semiconductor). On the other hand, the package stacking method may have advantages in terms of reliability and yields because individual packages, which have passed reliability testing, may be stacked together.
In a package stack having individual packages stacked together, a medium may be provided to electrically interconnect the individual packages. A typical medium is solder bumps.
A conventional package stack 10 using solder balls is shown in FIGS. 1A and 1B. FIGS. 1A and 1B are cross-sectional views of the package stack 10 taken in different directions. Referring to FIGS. 1A and 1B, the package stack 10 may have a structure in which two individual packages 11a and 11b may be stacked. The individual packages 11a and 11b may include molding resin 16 formed on a surface of a circuit substrate 12 and solder bumps 17a and 17b formed on an opposite surface of the circuit substrate 12. Inside the molding resin 16, an integrated circuit chip (hereinafter IC chip; not shown) may be attached and connected electrically to the circuit substrate 12.
The solder bumps 17a on the surface of the upper package 11a may interconnect the upper package 11a and the lower package 11b electrically. The solder bumps 17b on the surface of the lower package 11b may serve as external connection terminals when the package stack 10 is mounted onto a motherboard (not shown), for example.
The following example method may be employed to form the solder bumps 17a and 17b. The surface of the circuit substrate 12 may include a land (or site) on which the solder bumps 17a and 17b may be formed. Flux may be applied onto the land and solder bumps may be attached onto the flux, and then melted by a reflow process. Such bump forming techniques are well known in this art.
Although the conventional package stack 10 is generally thought to be acceptable, it is not without shortcomings. Some shortcomings may relate to the solder bumps 17a and 17b. 
The solder bumps 17b may provide mechanical and electrical connections between the package stack 10 and other devices(e.g., a motherboard). Such connections may be achieved via a reflow process. During the reflow process, however, the solder bumps 17a connecting the individual packages 11a and 11b may melt, which may cause a separation 18 (FIGS. 1A and 1B) of the connections between the solder bumps or a short circuit 19 (FIG. 1B) between adjacent solder bumps(19 in FIG. 1B). The same problem may for any given package within the package stack 10. As the number of packages included in the package stack increases, so may the number reflow processes, and thereby defects related to the solder balls may occur more frequently.
Another problem is that loose connections between balls may be caused by a warpage phenomenon of the circuit substrate 12. Each constituent element of the package stack 10 such as the circuit substrate 12, the molding resin 16 and the IC chip may have a different coefficient of thermal expansion. If a high temperature process like a reflow process is repeated, then the warpage phenomenon of the circuit substrate may arise. Accordingly, at both ends of the circuit substrate 12, where a relatively high warpage phenomenon may appear, the solder balls 17a may become loosened from the lower circuit substrate 12, which may lead to separated connections.